(1) Field of the Invention
The present invention relates to a circuit of a digital-to-analog converter and method for converting a digital signal into a corresponding analog signal suitable for assemblies of monolithic ICs.
(2) Description of the Background Art
A Japanese Patent Application First Publication (Unexamined) Sho 61-274424 (referred, hereinafter, to as reference 1) published on Dec. 4, 1986 exemplifies one of previously proposed structures of digital-to-analog converters (hereinafter referred simply to as D/A converters) of a resistance voltage divided type.
In the voltage divided type of D/A converters disclosed in the reference 1, a resistance ladder in which a 2.sup.n number of resistors R having equal resistance values are serially connected to an input terminal for receiving an n-bit digital input signal.
The resistance ladder causes a reference voltage V.sub.R applied across the resistance ladder to be equally divided into 2.sup.n to set each voltage for generating an analog quantity at each junction of the plurality of series connected resistors R. Each junction of the resistors R in the resistance ladder is also connected to one end of an analog switch, the total number of the analog switches being (2.sup.n -1). The other end of each analog switch is commonly connected to an output terminal of the analog quantity via a buffer. In addition, a decoder is provided in the D/A converter for receiving a digital input signal and providing a control signal for turning on or off each analog switch.
When the digital signal having a plurality of bits is inputted into the decoder and decoded by the decoder, one of the analog switches is turned on in response to the control signal derived from the decoder so that the analog quantity (voltage) corresponding to the digital input quantity appears on the output terminal of the D/A converter.
Another previously proposed D/A converter will be described below.
The other previously proposed D/A converter of a weighted resistance type (referred, hereinafter, to as reference 2) is provided with an operational amplifier having a grounded non-inverting input terminal and an inverting input terminal connected to parallel connected resistors R, 2R, 4R, 8R, 16R equal in number to the number of bits of the digital input signal. The output terminal of the operational amplifier serves as an output terminal of the D/A converter and is connected to the inverting input terminal via a resistor R.sub.f (=R/2).
The parallel-connected resistors and associated operational amplifier in the reference 2 constitute an addition circuit. Each resistor has a resistance value weighted as a binary weight such as R, 2R, 4R, 8R, 16R and 32R. Hence, if a resistance value of a resistor corresponding to 1 bit (Least Sgnificant Bit) is, for example, 1 K ohms (K.OMEGA.), the resistance value corresponding to n bit (Most Significant Bit) is set to 2.sup.n-1 K ohms (K.OMEGA.).
In addition, one contact of an analog switch is connected to each resistor, one of the other contacts thereof is connected to a reference volatge supply, and the remaining contact thereof is connected to the ground.
In the reference 2, when the digital input signal is inputted into the decoder and the decoder outputs the control signal, each switch is operated to connect the reference voltage supply to the corresponding resistor or connect the ground to the corresponding resistor in response to the control signal. Therefore, each switch which receives 1 bit code is operated to connect the reference voltage supply to the corresponding resistor so that the analog quantity corresponding to the sum of the resistors which receive the reference voltage supply appears on the output terminal.
In a still another previously proposed D/A converter of a current addition type (referred, hereinafter, to as reference 3), the resistor ladder is constituted by the plurality of resistors. Resistors having values of Rs are cascade connected from the reference voltage supply to the ground. One end of the cascade-connected (string) resistors R is grounded The other end of the cascade-connected resistors R is connected to the reference voltage supply. Each one end of the resistors Rs except the rightmost resistor R is connected with each one end of a plurality of other resistors having the values of 2R. Each other end of the other resistors 2Rs is connected with a corresponding analog switch. One contact of each analog switch is grounded and the other contact therefo is connected to the inverting input terminal of the operational amplifier. The non-inverting input terminal of the operational amplifier is grounded. The feedback resistor having the value of R is connected between the inverting input terminal and output terminal of the operational amplifier. A plurality of these resistors having the values of 2Rs are connected to respective junctions between the cascade connected resistors R. One of the other contacts of the respective switches is connected to the reference voltage supply and the remaining contact of the respective switches is connected to the ground. Each analog switch receives the control signal from the decoder and is turned to connect the reference voltage supply to the corresponding resistor having the value of 2R when the corresponding bit of the digital input signal indicates 1.
Accordingly, a current flow through the corresponding resistor of 2R.
At this time, binary weights such as I.sub.o /2, I.sub.o /4, I.sub.o /8 and so on are provided through the resistors having the values of 2Rs in an order from the position corresponding to the least significant bit of the digital input signal to the position corresponding to the most significant position. In addition, the analog switches corresponding to the respective bits indicated by 1 of the digital input are turned on so that the current flowing through the resistors having the values of 2R are added to the operational amplifier and the analog quantity corresponding to the digital input is outputted.
A further another previously proposed A/D converter of a voltage divided type (referred to as reference 4) will be described below.
The further previously proposed A/D converter (reference 4) is provided with a resistor ladder having the plurality of resistors. Resistors having the values of Rs are cascade connected. One end of the cascade-connected resistors Rs is grounded via a resistor having the value of 2R. The other end of the cascade-connected resistors Rs is connected to the non-inverting input terminal of the operational amplifier (buffer) and to the ground via a resistor having the value of 2R. Each junction of the cascade-connected resistors Rs is connected to one end of another resistor having the value of 2R. Each analog switch having one contact connected to the reference voltage supply and the other contact connected to the ground is connected to a corresponding resistor having the value of 2R.
When one of the analog switches corresponding to [1] of each bit in the digital input is switched to the reference voltage supply so that the voltage appearing on the corresponding junction is added at the non-inverting input terminal of the buffer of the other voltage at the other junction which corresponds to the other one of the analog switches which is operated according to the bit 1 of the other bits of the digital input. Therefore, only the resistor ladder of R-2R serves to output the analog quantity from the output terminal of the buffer which corresponds to the digital input.
A Japanese Patent Application First Publication (Unexamined) Sho 62-134 published on Jan. 6, 1987 (referred, hereinafter, to as reference 5) exemplifies a still another previously proposed D/A converter of a capacitor divided type.
In the reference 5, the D/A converter includes three capacitors having same capacitance values, seven switches, and one operational amplifier.
A first switch of the switches is turned off for the reference voltage to be charged in a first capacitor of the capacitors. At this time, a second capacitor is discharged by means of a fourth and fifth switches. In addition, a seventh switch causes a third capacitor to be discharged. Next, when the first, fourth, fifth and seventh switches are turned off and the second switch is turned on, an electric charge in the first capacitor is distributed into the second capacitor to provide V.sub.2 (a voltage across the second capacitor)=1/2.times.V.sub.R (reference voltage). If a MSB (Most Significant Bit) of the digital input indicates [1], the electric charge across the second capacitor is transferred into the third capacitor by means of the third switch. On the other hand, if the MSB indicates [0], the fourth switch causes the electric charge across the second capacitor to be discharged.
Thereafter, when the next significant bit indicates 0 and the second switch is turned on, the electric charge across the first capacitor is distributed to the second capacitor to provide V.sub.1 (voltage across the first capacitor)=1/4.times.V.sub.R. Thereafter, in the same way as described above, the electric charge across the second capacitor is discharged so as to correspond to the digital input or transferred into the third capacitor.
In this way, the voltage at the output terminal of the operational amplifier indicates 11/16 V.sub.R (1/2 V.sub.R +1/8 V.sub.R +1/16 V.sub.R) when the digital input signal indicates 1011.
The analog quanity corresponding to the digital input is sequantialy outputted from the output terminal by the repetition of the above-described operation until the LSB (Least Significant Bit) is reached.
The above-described five references have the following problems respectively.
That is to say, in the reference 1, the number of resistors constituting the resistor ladder must equal 2.sup.n, n beingb the number of bits of the digital input. For example, if the digital input is constituted by 8 bits, 256 number of the resistors are required. As the number of bits increases, the area they occupy on a semiconductor substrate becomes increased. For example, in the case of the 8-bit digital input, about 3 mm per 5 .mu.m rule must be required. Therefore, it becomes difficult to carry out an assembly of monolithic IC device.
In addition, in the reference 2, binary weight is provided for each resistor. If the resistor corresponds to one bit, the resistors corresponding to n bit indicate 2.sup.n-1 k.OMEGA.. For example, in the case of 8 bits, one of the resistors which corresponds to 8th bit (MSB) require 128 k.OMEGA.. Therefore, it becomes difficult to assemble each resistor having such a resistance value on the same semiconductor substrate.
Furthermore, if the analog switch connected to each corresponding resistor is formed of, e.g., MOSFETs and on resistance of the MOSFETs is reduced to a negligible degree with respect to each resistor for which the corresponding resistance value is provided, an extremely large area is required for a single chip. It is very difficult to assemble the MOSFETs having such large areas as described above and having the equal number to the number of bits in the digital input on the same semiconductor substrate.
The switches in the references 3 and 4 have the same problems as those switches in the reference 1.
It is necessary, in the case of the reference 5, to provide a large, capacitance, i.e., a large area for each capacitor to provide a high accuracy of the D/A converter output. This contributes the difficulty in assemblies of the capacitors in the same semiconductor substrate. In addition, since the analog quantity is determined from a floating node of each of the first and third capacitors, a noise-free operation of the D/A converter in the semiconductor substrate cannot be ahieved.